G-1: Analysis of TID testing of a statistically large quantity of parts
J. Voegtli1, R. Sharp1, L. Oswald2, N. Hong2, B. Archer2
1 Radtest Ltd, United Kingdom
2 University of Oxford, United Kingdom
1,000 LM239N quad comparators (two manufacturers, ten date codes) have undergone TID testing to improve the definition of the optimum sample size for such a test. This paper presents a statistical analysis of the results.
G-2: FPGA Benchmarking structures dedicated to TID parametric degradation evaluation
G. Bricas1, G. Tsiligiannis1, A. Touboul1, J. Boch1, T. Maraine1, F. Saigne1
1 University of Montpellier, France
This paper presents a simple, cost-effective and efficient methodology to evaluate and compare parametric degradation of FPGA performance induced by TID. X-ray radiation test results on three FPGA families are presented, compared and discussed.
G-3: Time-of-flight SEU Cross-section Measurements for 1-800 MeV neutrons and the Soft-error Rates at 18 MeV Proton Cyclotron-driven Neutron Source
H. Iwashita1, Y. Hiroshima1, Y. Okugawa1, R. Kiuchi2, H. Sato2, T. Kamiyama2, F. Michihiro2, Y. Kiyanagi3
1 NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Japan
2 Hokkaido University, Japan
3 Nagoya University, Japan
We measured the energy-dependent neutron-induced SEU cross-section for 1-800 MeV by the time-of-flight technique. Furthermore, we calculated the soft-error rates at a neutron field from an 18 MeV proton cyclotron-driven neutron source using this cross-section.
G-4: Impact of experimental conditions for the occurrence of stuck bits in commercial SDRAM
J. Guillermin1, B. Vandevelde1, N. Chatry1, M. Poizat2
1 TRAD, France
2 ESA, Netherlands
Different commercial SDRAM were irradiated under protons in order to assess their sensitivity to stuck bits and determine the experimental conditions which are favorable to their occurrence.
G-5: Processor SER Estimation with ACE Bit Analysis
T. Hsu1. D. Yang1, W. Liao2, M. ltoh3, M. Hashimoto4, J. Liou1
1 National Tsing Hua University, Taiwan
2 Kochi University of Technology, Japan
3 Tohoku University, Japan
4 Kyoto University, Japan
We proposed to estimate the SER by considering architecturally correct execution (ACE) bits of memory elements in a processor. In an irradiation experiment, the estimated SER has a good consistency with measured SER.
G-6: High-energy hadron testing and in-orbit single-event latchup predictions and boundaries
A. Coronetti1, R. Garcia Alía1, A. Javanainen2, F. Saigné3
1 CERN, Switzerland
2 University of Jyväskylä, Finland
3 University of Montpellier, France
Boundaries for the application of a volume equivalent LET approach to predict the SEL in-orbit rate based on the SEL cross-section retrieved from high-energy hadron testing are discussed along with upper bounds for zero events.
PG-1: Lot-to-lot variability TID effects on COTS BJT
F. Krimmel1, T. Borel1, A. Costantino1, M. Muschitiello1, F. Tonicello1, A. Pesce1
1 ESA - ESTEC, Netherlands
This work presents measurements and lot-to-lot variability analysis of the TID degradation of the gain on three COTS BJT part types (BC817, BC847 BC857)
PG-2: Testing and Validation Methodology for a Radiation Monitoring Systems for Electronics in Particle Accelerators
A. Zimmaro1,2, R. Ferraro1, J. Boch2, F. Saigné2, R. Garcia Alía1, A. Masi1, S. Danzeca1
1 CERN, Switzerland
2 University of Montpellier, France
In this work, a methodology for the design and validation of a novel wireless battery powered radiation tolerant monitoring system in particle accelerators is presented.
PG-3: Proton Cross-Sections from Heavy-lon Data: A Review of the Models
D. Hansen1, D. Czajkowski1, B. Vermeire1
1 Space Micro, USA
This paper reports on the calculation of proton SEU cross-sections using heavy-ion data using a numb. Calculations are checked using data on proton and heavy-ion cross-sections from the published literature.
PG-4: PTA based availability analysis of the effects of blind scrubbing of UAV-UAV communication using SRAM based FPGAs
M. Abdelhamid1, A. Attallah1, M. Ammar1, O. Ait Mohamed1
1 Concordia University, Canada
This paper computes the worst-case failure for serial UAV communication components using SRAM FPGAs. Furthermore, our framework implements priced timed automata models to execute the blind scrubbing technique and analyze UAV-UAV communication availability at different scrubbing intervals and durations.
PG-5: Methodical Approach for SEL Tolerance Confirmation of CMOS ICs at Low Temperatures
M. Novikova1, A. Novikov1, A. Pechenkin1, V. Lukashin1, E. Oblova1, A. Gritsaenko1, D. Protasov1, A. Tararaksin1
1 Specialized Electronic Systems, Russian Federation
An approach for SEL sensitivity estimation using heavy ions at room temperature and laser facilities at both room and subzero temperatures is proposed. The results of comparison approach approbation are also presented.