Technical Session C

RADECS 2021

RADECS 2021 - Preliminary Technical Program

Wednesday, September 15, 2021 (starts at 9.10 h)

RADECS 2021 - Session C

Single Event Effects: Mechanisms & Modelling

Session Co-Chair:

Adrian Ildefonso, U.S. Naval Research Laboratory
Arto Javanainen, University of Jyväskylä

ORAL PRESENTATIONS

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V. Wyrwoll1, K. Roed1, R. Garciaalia2, B. Delfs3, A. Coronetti4, W. Farabolini2, A. Gilardi2, R. Corsini2

1University of Oslo, Norway
2European Organization for Nuclear Research (CERN), Switzerland
3University Clinic for Medical Radiation PhysicsMedical Campus Pius Hospital, Carl von Ossietzky University, Germany
4CERN, Switzerland

 

Single Event Effects (SEEs) induced by high energy pulsed electrons in a ESA SEU monitor are discussed. Measurements with high energy electrons have been performed at VESPER (CERN) focusing on instantaneous fluxes and dose rates.


A. Feeley1, Y. Xiong1, N. Pieper1, D. Ball1, B. Bhuva1

1Vanderbilt University, USA


SE rates for a 7-nm bulk FinFET node are investigated at NTV supply voltage for different VT options. Results show minimal differences at close-to-nominal voltages, and that LVT had lowest SEU cross- section at NTV


 

C. Martinella1, P. Natzke2, R. Garciaalia3, Y. Kadi3, U. Grossner2, A. Javanainen4

1University of Jyväskylä, CERN, APS - ETH Zurich, Finland
2APS - ETH Zurich, Switzerland
3CERN, Switzerland
4University of Jyväskylä, Finland

 

Heavy-ions induce latent damage in SiC power MOSFETs, involving the gate oxide and the SiC crystal lattice. The failure site was investigated using plasma SEM-FIB analysis. An overview of the heavy-ion SEEs is given.


 

POSTERS

D. Truyen1, E. Leduc2, L. Montagner2, M. Briet2, A. Collange3

1MICROCHIP, France
2Microchip technology, France
3Microchip Technology, France

 

This work presents a new approach of a predictive SEL modeling by neural networks, covering the CMOS technology nodes from 500nm up to 22nm. The SEL Model is validated by experimental results.


 

S. Alberton1, N. Medina1, N. Added1, V. Aguiar1, M. Guazzelli2, R. Baginski2

1Universidade de Sao Paulo, lnstituto de Fisica, Brazil
2Centro Universitário FEI, Brazil

 

The Lackners' theory for avalanche multiplication provides physical interpretation for the model parameters, although obtaining them through experimental methods is necessary. Comparing computational simulations and experimental measurements, the Lackners' impact ionization coefficients were estimated.


 

X. Zhou1, Y. Jia1, D. Hu1, Y. Wu1, Y. Zhao1

1Beijing University of Technology, China


This paper presents the experimental characterization of SiC MOSFETs exposed to the heavy­-ion irradiation. Different leakage paths related to the drain bias used during the tests are observed, suggesting different damage sites in the devices, which can be further verified through the post-irradiation measurements. TCAD simulations are utilized to explore the failure mechanisms. lt is shown that the gate oxide rupture firstly occurs in the middle of the JFET region, while gradually spreads to the channel region with the increase of biased drain voltage, and terminates at the source region eventually. The findings in this paper demonstrate that more attentions should be paid on the heavy-ion induced gate oxide damage before SiC MOSFETs could act as a drop-in replacement of Si-based counterparts in avionic applications.


 

N. Pieper1, Y. Xiong1, A. Feeley1, G. Walker1, B. Bhuva1, R. Fung2, S. Wen2

1Vanderbilt University, USA
2cisco, USA

 

Location and temperature characteristics of micro-latchups at the 7-nm bulk FinFET technology is investigated. Thermal images show that micro-latchup locations are spatially clustered and are removed serially when supply voltage is reduced.