C-1: Highly Pulsed Electron Beam induced SEU Effects in a SRAM memory
V. Wyrwoll1, K. Roed1, R. García Alía2, B. Delfs3, A. Coronetti4,5, W. Farabolini2, A. Gilardi2, R. Corsini2
1 University of Oslo, Norway
2 European Organization for Nuclear Research (CERN), Switzerland
3 University Clinic for Medical Radiation Physics, Medical Campus Pius Hospital, Carl von Ossietzky University, Germany
4 CERN, Switzerland
5 University of Jyväskylä, Finland
Single Event Effects (SEEs) induced by high energy pulsed electrons in a ESA SEU monitor are discussed. Measurements with high-energy electrons have been performed at VESPER (CERN) focusing on instantaneous fluxes and dose rates.
C-2: SE Performance of D-FF Designs with Different VT Options at Near-Threshold Supply Voltages in a 7-nm Bulk FinFET Technology
A. Feeley1, Y. Xiong1, N. Pieper1, D. Ball1, B. Bhuva1
1 Vanderbilt University, USA
SE rates for a 7-nm bulk FinFET node are investigated at NTV supply voltage for different VT options. Results show minimal differences at close-to-nominal voltages, and that LVT had lowest SEU cross-section at NTV.
C-3: Heavy-lon lnduced Latent Damage in SiC Power MOSFETs
C. Martinella1,2,3, P. Natzke2, R. García Alía3, Y. Kadi3, U. Grossner2, A. Javanainen1
1 University of Jyväskylä, Finland
2 APS - ETH Zurich, Switzerland
3 CERN, Switzerland
Heavy-ions induced latent damage in SiC power MOSFETs, involving the gate oxide and the SiC crystal lattice. The failure site was investigated using plasma SEM-FIB analysis. An overview of the heavy-ion SEEs is given.
PC-1: A Neural Network Approach for Single-Event Latchup Prediction Based on TCAD Simulations in CMOS Technology
D. Truyen1, E. Leduc1, L. Montagner1, M. Briet1, A. Collange1
1 Microchip Technology, France
This work presents a new approach for predictive SEL modeling by neural networks, covering the CMOS technology nodes from 500nm down to 22nm. The SEL model is validated by experimental results.
PC-2: Heavy-lon-lnduced Avalanche Multiplication in Low-Voltage Power VDMOSFET
S. Alberton1, N. Medina1, N. Added1, V. Aguiar1, M. Guazzelli2, R. Baginski2
1 Universidade de São Paulo, lnstituto de Física, Brazil
2 Centro Universitário FEI, Brazil
The Lackners' theory for avalanche multiplication provides physical interpretation for the model parameters, although obtaining them through experimental methods is necessary. Comparing computational simulations and experimental measurements, the Lackners' impact ionization coefficients were estimated.
PC-3: Heavy-ion lnduced Gate Oxide Rupture in SiC MOSFETs
X. Zhou1, Y. Jia1, D. Hu1, Y. Wu1, Y. Zhao1
1 Beijing University of Technology, China
This paper presents the experimental characterization of SiC MOSFETs exposed to the heavy-ion irradiation. Different leakage paths related to the drain bias used during the tests are observed, suggesting different damage sites in the devices, which can be further verified through the post-irradiation measurements. TCAD simulations are utilized to explore the failure mechanisms.
PC-4: Micro-Latchup Location and Temperature Characterization in a 7-nm Bulk FinFET Technology
N. Pieper1, Y. Xiong1, A. Feeley1, G. Walker1, B. Bhuva1, R. Fung2, S. Wen2
1 Vanderbilt University, USA
2 Cisco, USA
Location and temperature characteristics of micro-latchups at the 7-nm bulk FinFET technology are investigated. Thermal images show that micro-latchup locations are spatially clustered and are removed serially when supply voltage is reduced.
PC-5L: Isotopic enriched and natural SiC junction barrier Schottky diodes under heavy ion irradiation
K. Røed1, D. Eriksen2, B. Ceccaroli2, C. Martinella3, A. Javanainen3, S. Reshanov4, S. Massetti5
1 University of Oslo, Norway
2 Isosilicon AS, Norway
3 University of Jyväskylä, Finland
4 II-VI Kista AB, Sweden
5 ESA-ESTEC, Netherlands
The radiation tolerance of isotopic enriched and natural SiC JBS diodes are compared under heavy ion irradiation. The results indicate a marginally lower onset of degradation events for the monoisotopic type under reverse biased conditions.