Technical Session F

RADECS 2021

RADECS 2021 - Preliminary Technical Program

Tuesday, September 14, 2021 (starts at 14.20 h)

RADECS 2021 - Session F

Hardening Techniques

Session Co-Chair:

Daisuke Kobayashi, ISAS/JAXA
Maxim Gorbunov, SPELS/NRNU MEPhl

ORAL PRESENTATIONS

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L. Clark1, A. Duvnjak1,  M. Cannon2, J. Brunhaver1,  S. AgarwaI2, J. Manuel2, M. Marinella2

1 Arizona State University, USA
2 Sandia National Laboratories, USA

 

A radiation hardened microprocessor design implemented on a 12-nm bulk finFET CMOS process is presented. The processor uses a combination of circuit redundancy and micro­-architecture for hardening.


L. Garcia-Astudillo1, A. Lindoso1, L. Entrena1, H. Martín1, M. Garcia-Valderas1

1 Universidad Carlos III de Madrid, Spain
 

We propose a Scaled RPR approach for multi-stage circuits and analyze mitigation tradeoffs. FFT designs were tested with low-energy protons and fault injection. This approach achieves error mitigation with good precision, while reducing the overhead.


A. Portaluri1, C. De Sio1, S. Azimi1, L. Sterpone1

1 Politecnico di Torino, ltaly


We developed a domain based isolation design flow for the mitigation of SEU effects an SRAM-based FPGAs. Fault injection experimental analysis an TMR circuits mapped on APSoC demonstrates an improvement of 44% versus traditional mitigation techniques.


 

M. Peña Fernández1, A. Serrano-Cases2, A. Lindoso3, S. Cuenca-Asensi2, L. Entrena3, A. Martinez-Álvarez2

1 Arquimea lngeniería SLU, Spain
2 University of Alicante, Spain
3 University Carlos III of Madrid, Spain

 

A new hybrid soft error mitigation technique for multi-core processors, validated with low energy proton irradiation, based an multi-threaded lockstep and a custom hardware interfacing the trace port, is presented.


 

POSTERS

L. Tansini1, P. Rech1

1UFRGS, Brazil

 

We evaluate the impact of safety-critical Model-Based Design (MBD) code generation tools in programs reliability. We compare Manual, Simulink, and Scade implementations. ln general MBD tools reduce the SDC rate but increase the DUE rate.


 

S. Thomet1,2, S. De-Paoli1, F. Ghaffari2, J. Daveau1, V. Bertin1, F. Abouzeid1, O. Romain2, P. Roche1

1 STMicroelectronics, France
2 ETIS Lab - ENSEA, France

 

This paper presents a fail-reason capturing intellectual property. lntegrated in a system-on-a-chip, it provides diagnostic information about the origin of failures thanks to the combination of trace events buffering and error detection with triggering mechanisms.


 

A. Dorise1, C. Alonso1, A. Subias1, L. Travé-Massuyès1, L. Baczkowski2, F. Vacher2

1 LAAS-CNRS, France
2 CNES, France

 

This paper describes a new method to detect high current event caused by space radiation. Results of machine learning algorithms used on data sets created for this particular study are discussed.