Radiation Hardness Assurance

Ionizing Radiation and Radiation Hardness in Analog Integrated Circuits: Recent X-Ray testing

Varvara Bezhenova, Alicja Michalowska-Forsyth
Graz University of Technology, Institute of Electronics, Inffeldgasse 12/I, Graz 8010, Austria


Development of radiation hardened integrated circuits (ICs) is a long iterative process. Radiation hardness assurance of such ICs involves multiple comparisons between various device and circuit topologies. In this talk we present the challenges of this process on an example of two test ICs designed at the Institute of Electronics at Graz University of Technology and fabricated in a commercial 180 nm CMOS process.

These ICs were tested against the effects of total ionizing dose at three different X-ray facilities, available in Austria.  The comparison of the test results from different facilities is additional challenging task in the radiation hardness assurance procedure. This includes comparison of the dose rate estimation with different dosimetry tools available at these facilities as well as comparison of TID effects on ICs, irradiated at different X-ray sources.


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[6] V. Bezhenova and A. Michalowska-Forsyth. “Aspect ratio of radiation-hardened MOS transistor”, e&i Elektrotechnik und Informationstechnik Feb. 2018 vol 135, pp 61-68.

[7] M. Auer and V. Bezhenova. “A radiation hard curvature-compensated bandgap voltage reference”, e&i Elektrotechnik und Informationstechnik Feb. 2018, vol 135, pp  3-9.


Authors would like to thank the team of MedAustron non-clinical research department for granting the access to research facilities and equipment.