Radiation Hardness Assurance

Radiation Hardening of Integrated Circuits


Varvara Bezhenova, Alicja Michalowska-Forsyth
Graz University of Technology, Institute of Electronics, Graz 8010, Austria


An approach to radiation hardening of MOS transistors for use in analog integrated circuits will be presented. In this procedure the integrated MOS devices and circuits are designed for increased robustness and then fabricated on a prototype IC. The electrical tests need to be run to check the conformity to simulation results before stress with the ionizing radiation. The prospects for radiation hardness assurance testing against the effects of the total ionizing dose will be also discussed. In particular for a large number of devices and analog blocks integrated on a single circuit the measurement optimization in terms of time, complexity and parasitics is a big issue for radiation hardness assurance testing.


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V. Bezhenova, A. Michalowska-Forsyth „Total ionizing dose effects on MOS transistors fabricated in 0.18um CMOS technology“, 2016 Asia-Pacific International Symposium on Electromagnetic Compatibility, (APEMC), Shenzhen 2016, pp. 366-369.

J. Benfica et al., „Analysis of SRAM-based FPGA sensitivity to combined EMI and TID-imprinted effects“, IEEE Transactions on Nuclear Science, vol. 63, no. 2, pp. 1294-1300., April 2016.


The authors gratefully acknowledge the support of research projects at the Institute of Electronics by: The Austrian Research Promotion Agency (FFG) and ams AG.