Pre-charge analysis in Sidewall Spacer with respect to Ionizing Radiation
Tommaso Vincenzi1,2, Gregor Schatzberger1, Alicja Michalowska-Forsyth2
1ams AG, 2Graz University of Technology
Non-Volatile Memories (NVM) suffer from radiation damage in the same way regular MOS devices do, having to withstand Total Ionizing Dose (TID) and Single Events (SE). Nowadays, most of the commercially available solutions for NVMs are charge based. This means that the information is stored as either positive or negative charge within a certain storage element, either it being a conductive layer, such as in Floating Gate (FG) devices , or a non-conductive one, as in Charge Trapping devices [2-3].
The presentation analyzes the Sidewall Spacer (SwSpc) Memory BitCell , compliant with standard CMOS process, and expands the works performed in . This type of device is more robust compared to standard FG because it uses a charge-trapping mechanism rather than a conductive layer to preserve the charge. In particular, due to the cost benefit and the high-reliability to TID, the SwSpc is particularly suitable both for medical and consumer applications, normally separate and independent. This work analyzes how the charging conditions, i.e. the amount of charge in the nitride spacer after a program operation, influences the tolerance of the BitCell to ionizing radiation. Multiple chips have been tested under a tungsten X-ray tube up to 500krad to sample the response of the cells.
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 T. Vincenzi, G. Schatzberger and A. Michalowska-Forsyth, "Program Time Effects on Total Ionizing Dose Tolerance of Sidewall Spacer Memory Bit Cell," 2019 Austrochip Workshop on Microelectronics (Austrochip), Vienna, Austria, 2019, pp. 55-58
The authors thank Alex Costa, Heinz Pernegger, Johannes Fellner and Bernd Deutschmann for the support on the project. A special thanks to MedAustron research center for the support on the irradiation of devices.