Latch-up Detection and Mitigation Strategies
B. Seifert1, T. Hörbe1, E. Ceribas1
1FOTEC Forschungs- und Technologietransfer GmbH, Wiener Neustadt, Austria
FOTEC has been developing COTS-based (Commercial Off the Shelf) electronics for space application for more than 10 years. As space is a harsh environment, extensive qualification testing is required during the development process. This includes environmental testing, such as thermal-vacuum, vibration and shock, as well as EMI (Electromagnetic Interference) and radiation testing. The latter is again split into TID (Total Ionizing Dose) and SEE (Single Event Effect) test cases.
EEE (Electrical, Electronic and Electromechanical) components are qualified for commercial, industrial, automotive, military or space application with increasing reliability and costs but decreasing availability. Therefore, FOTEC attempts to utilize mostly automotive and military parts. Also, up-screening is possible to qualify components for higher reliability classes. This presentation will focus on different approaches regarding circuit design to increase the reliability of the total system without the necessity to use space-qualified components. The focus is laid on transient latch-up hazards, where fast (charged) particles can trigger the parasitic thyristor structure of semiconductors which leads to high current draw. This in turn, can overheat the die itself or permanently break thin tracks in it.
It is possible to use current-limiting resistors or PTC (Positive Temperature Coefficient) thermistors to reduce the current draw by a component, even when it is in latch-up condition. For power components, such MOSFETs in half- or full-bridge configuration, different approaches have to be taken to avoid a significant decrease in efficiency. In this scenario, fast-acting temperature surveillance in the near vicinity of the critical components is implemented.